ProgrammerSought

System Operation

ARM processor

ABLITE bus connection

Choice of boot method

  - Boot from embedded ROM (default)

  - Boot from eMMC flash

  - Boot from SPI or Flash

Memory Organization

Internal 224 KB SRAM for IRAM and DRAM

Embedded 64 KB ROM for decoder and system code

Processor

ARM Cortex M3 Low Power Core

  - Thumb instruction set subset

  - Bank Stack Pointer (SP)

  - Hardware slice instructions, SDIV and UDIV (thumb 32-bit instructions)

  - Handler and thread mode

  - Thumb and debug status

  - Interruptibility - persistent LDM/STM, PUSH/POP with low interrupt latency

  - Automatic processor state save and restore for low latency Interrupt Service Routines (ISRs)

Nested Vectored Interrupt Controller

  --26th external interruption

  - 32 levels of interrupt priority

Clock & Power Management

Monolithic phase-locked loop, the system main clock can be the phase-locked loop clock or the occ input clock.

Supports different main clock and internal AHB bus clock ratios: 1:1, 1:2, 1:3, 1:4, up to 1:8 modes

Supports different ratios of AHB bus clock and ARM system clock: 1:2, 1:3, 1:4, up to 1:8 modes

Supports different AHB bus clock and ARM APB bus clock ratios: 1:1, 1:2, 1:3 and 1:4 mode

100 MHz maximum frequency for ARM cores

Hardware Accelerator for MP3 decode

MP3 imdct 36 calculation module

MP3 Subband Synthesis Module

Memory Interface

external memory controller

  - Supports 4 chip select NAND flash

  - Support 24/40/60 bit ECC error correction

  - Supports 8-bit data width to external NAND

SD/MMC Controller

  - SD/MMC SPI mode/1-bit mode/4-bit mode

  - Support for Multimedia Card Specification Version 4.41

  - Support SD Memory Card Specification Version 3.0

  - Supports safe digital I/O (SDIO Version3.0)

  - Card clock rate up to pclk, rescale sd/mmc clock (Pclk) with 8-bit prescale register in scu block.

VIDEO interface

LCD controller

  - Compatible with single-chip LCD panel

  - Up to 8 lcd data output buses

DMA Controller

DMA controller in chip

  - Supports 3 DMA channels, 7 external requests

  - Supports incremental and fixed addressing modes

  - Support hardware and software trigger DMA transfer mode

  - Supports error interrupts, transfers - complete interrupts

  - When the transmitted data is inconsistent with the source burst, the last data will be transmitted in a single burst.

  - Supports configurable channel priority

USB interface

USB2.0OTG controller and PHY

Operates in high-speed and full-speed modes.

Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)

Supports 6 endpoints, one control endpoint, two input/output endpoints, one IN endpoint

Support 4 channels in host mode, support large-capacity transmission

Low speed Peripheral interface

I2C controller

  - Support master-slave mode of I2C bus

  - Software programmable clock frequency and transfer rate up to 100 Kbit/s in standard mode and up to 400 Kbit/s in fast mode

  - Supports 7-bit and 10-bit addressing modes.

I2S

Support for mono/stereo audio files

Supported audio resolution: 8, 16 bit

Supports audio sample rates from 8 KHz to 48 kHz

Supports i2S left-justified and right-justified digital serial data formats

PWM

3-channel built-in 16-bit timer

0~100% duty cycle PWM signal generation

Rescale count clock (PCLK) using 8-bit prescale register in scu block

SPI master

Serial-Master Action-Enable Serial Communication with Serial-Slave Peripherals

DMA Controller Interface - Implements an interface to a DMA controller using a handshake interface for transfer requests

Support interrupt interface, independent mask interrupt controller

A hardware slave select line

Dynamic Control of Serial Bit Rate for Data Transmission

GPIO

Supports 28 individually programmable input/output pins

28 GPOs with external interrupt capability

Timer

Built-in 24-bit timer module

Supports two operating modes

Uart

Amba apb interface - allows easy integration into synthesizable components of amba 2 implementations.

DMA Controller Interface - An interface that enables a DMA controller on the AMBA bus using the handshake interface for transfer requests

Interrupt interface is supported to interrupt the controller

Analog IP interface

 AUDIO-DAC

 - 24-bit audio DAC with headphone amplifier

 - Ultra low static current

 - No POP noise

 - High Efficiency Class G Headphone Amplifier

 - Asynchronous with different sample rates

MIC amplifier

20 dB Low Noise Boost Amplifier

Low Noise Programmable Amplifier for MIC Input

ADC Converter

4-channel single-ended 10-bit 1 msps successive approximation register analog-to-digital converter

DCDC

1.2V default output voltage setting

Compensation control in current mode

100 mA peak output current

Forced PWM operation

Adjustable output voltage

1.2MHz operating frequency

Integrated cout discharge switch

This article is excerpted from the RKnanoC datasheet .