False sharing of concurrent programming

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1. CPU cache and false sharing

CPU cache and coherence

In the introduction of CPU cache and memory barrier , the CPU follows cache consistency when reading data to solve the problem of data inconsistency in the cache, which is briefly described as follows:

  • The CPU cache includes L1-L3 Cache cache, each cache Cache is stored in segments (line), that is, cache segment (Cache line)
  • According to the consistency of the cache, in the case of a multi-core CPU processor, when one of the CPUs writes to the cache where it is located and notifies other CPUs, the other CPUs will invalidate the cache and read the data in the main memory. Copy the data of consecutive variable addresses into the cache segment

Definition of false sharing and its causes

  • false sharing

    • Premise: In a multi-core CPU processor, each CPU will have corresponding cache data, and the cache segment caches the data stored continuously. Assuming that there are L1 and L2 caches on the multi-core processor, then at this time, the L1 and L2 caches The segment will copy a copy of the variable data of a continuous memory address from the main memory, realize one read of the main memory, and then read the data of the cache segment multiple times, that is, the CPU cache is implemented for data variables with continuous memory addresses. Write once, read many times
    • Pseudo-sharing scenario: When one of the CPUs writes a variable data whose memory address is discontinuous, because the CPU follows cache consistency, the other CPU needs to read the variable data at this time, because the variable data memory address The discontinuity causes the data not to exist in the read cache segment and is loaded from the main memory, that is to say, when the data variable is written to the cache segment, it will fail before it has time to read.
    • Influence: The result of pseudo-sharing is that the CPU cache does not take effect, and the cache is not hit. At the same time, the consistency of the cache destroys the principle of reading the CPU's first-level cache. The reason is that the CPU cache will be cached when concurrent threads perform write operations Failure, will also cause false sharing
    • The above is a phenomenon of false sharing, that is, when the CPU writes more, the CPU cache does not really play a role.

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