ProgrammerSought

This article introduces the MT6166 specifications and manuals for engineers to learn or refer to. Other related technical information can be found in the yiniu.com forum.

The MT6166 is an RF transceiver targeting high-speed 2G/3G-FDD/TDD multi-mode smartphones and 40 nm CMOS tablets. The RF transceiver functionality is fully integrated.

MT6166 system block diagram and application diagram

MT 6166 system block diagram

At present, this product considers using wire bond TFBGA.

Within the operating range, the IC operates according to the functional description.

The reference clock subsystem is shown in the following figure.

This integrates the core 26 MHz Xtal oscillator (DCXO), AFCDAC and 32 kHz low power mode. In addition, this system also integrates all external and internal clock buffers.

The operating mode (internal DCXO or external VCTCXO) is selected by inputting XMODE from the baseband and has the following functions

In crystal mode, Xtal is directly connected between XO1 and XO2.

In VCTCXO mode, the XO2 pin is reconfigured as the AFCDAC output and XO1 is configured as the VCTCXO clock input pin.

Since the state of XMODE is locked into the module, a pin state "capture" scheme on the power supply can be used for baseband configuration if desired.

http://bbs.16rd.com/thread-13344-1-1.html

This is an integer-N PL that generates a 416 MHz clock for the TX DAC and Rx ADC. It runs on 26mhz (16x26mhz=416mhz) and 416mhz clocks and produces some 26mhz clocks for sys. Synchronize from the feedback path (eg tx dynamic clock 26mhz) to synchronize with the 416mhz clock. Also, the TX ADC (power detector) with 26 MHz clock is from this block.

The transmitter consists of 5 output ports. The TX_LB2 and TX_HB1 ports are multi-mode ports that can support 2G or 3G depending on the application circuit on the phone. tip. Maximum TX output power>0dBm. The total TX gain dynamic range is 78 dB for RF and 8 dB for BB. Power detection circuitry is also included on the power region where the PA gain mode changes for better power accuracy. To ensure power detection accuracy, the PCB trace to the Det pin should not be too close to the TX output signal trace.

The receiving circuit is all regulated by the internal LDO. Direct conversion/lif receivers contain all active circuits supporting a complete receive chain of single cell (SC)/dual cell (Dc). ) 3G WCDMA, 3G TDSCDMA and 2G GSM/GPRS/EDGE(GGE) mode reception. This path contains a total of 7 LNAs (low noise amplifiers). The first 4 LNAs support 3G, 1/2/3/4/5/6/8/9; the fifth LNA supports T; the last 2 LNAs support GGE low band (GSM 850/900) and GGE high band (DCS 1800/ PCS 1900). The GGE high-band LNA also supports TDD B33/B34/B39.

The receiver can also be used on platforms that support dual-phone operation. In dual-phone applications, the first 4 LNAs also support TDD B33/B34 and 2G bands via common band. As listed in the table below, there are 8 scenarios for single- and dual-conversation applications. Three-wire control is used to select one of these schemes for proper operation.